The present invention generally relates to pipeline analog to digital (A/D) converters and, more particularly, to a pipeline A/D converter digital logic correction circuit with a reduced number of shift registers.
There is an ever present demand for analog to digital (A/D) converters that accurately convert an analog voltage signal into a digital representation. There is also a need for faster A/D converters that use less power and have smaller areas on an integrated circuit.
FIG. 1 illustrates a conventional pipeline analog to digital (A/D) converter 10. The A/D converter 10 converts an analog electrical input signal (VIN) into a digital representation of the analog signal (Dout). The illustrated example is a 4-bit A/D converter, but it should be understood that a resolution of more or less bits may be implemented with the addition or removal of converter stages. Therefore, the resolution of the A/D converter will sometimes be referred to an N-bit A/D converter, where N represents the number of digital output bits. The A/D converter 10 has an analog signal input 12 provided on an initial stage. The initial stage is a sample-and-hold amplifier (SHA) 14. The SHA 14 samples the analog input signal and holds the sampled voltage, or Vs/h, for the next stage of the pipeline A/D converter 10 at an SHA output 16. The stage following the SHA 14 is a multiplying digital to analog converter (MDAC) 18. MDAC 18 stages are added to the pipeline to increase the number of output bits.
With additional reference to FIG. 2, each MDAC 18 has an analog input 20 and an analog output 22. Each MDAC 18 performs analog to digital conversion of an MDAC input signal, VI, applied to the analog input 20. Each MDAC 18 also calculates an amplified residue signal, Vres, which is output for the next stage at the analog output 22. The number of MDAC 18 stages is determined by the desired resolution of the A/D converter 10, or the value of N. The number of MDAC 18 stages is equal to N minus two. In the example, the resolution is four bits. Therefore there are two MDAC 18 stages, referred to as MDAC1 (reference numeral 24) and MDAC2 (reference numeral 26). The SHA output 16 is connected to the analog input 20 of MDAC1. The analog output 22 of MDAC, is connected to the analog input 20 of MDAC2. Therefore, the VI of each MDAC 20, other than MDAC, which receives Vs/h, is the Vres of the preceding MDAC 18, also referred to herein as Vresm where m stands for the MDAC 18 generating the output signal. The analog output 22 of the last MDAC 18, which is MDAC2 in the example, is connected to an input 28 of a last stage 30. The last stage 30, which will be discussed in more detail below, has no analog output.
Each MDAC 18 and the last stage has two digital outputs 32, 34 for providing one bit of resolution and one bit for correcting error. The bits are generically referred to as b1 and b0, or, for a specific MDAC 18, are referred to as bm1 and bm0 where m stands for the MDAC 18 generating the output signal or the last stage 30. It is noted that MDAC1 generates b11 and b10 with some degree of errors MDAC2 generates b21 and b20 with some degree of error and so forth. With additional reference to FIG. 4, the last stage 30 of the illustrative four bit A/D converter 10 generates b31 and b30, where b30 is the least significant bit (LSB) and b31 is used to correct error generated by MDAC2 by adding b31 and b20. As illustrated, b21 is added to b10 to correct error generated by MDAC1. In general, therefore, bm1 is used to correct the error generated by MDACmxe2x88x921.
Still referring to FIGS. 1 and 2, each MDAC 18 has a 1.5 bit analog to digital converter (ADC) 36 for generating b1 and b0 from VI. Table 1 is a definition table for the values of b1 and b0 with respect to VI for the MDAC 18. It is noted that xc2x1Vr is the full scale range of the ADC 36.
Once b1 and b0 are generated by the ADC 36 they are output at digital outputs 32, 34 and also input into a 1.5 bit digital to analog converter (DAC) 38. The DAC 38 converts b1 and b0 into an analog signal, or VDAC, used in the calculation of Vres. Table 2 is a definition table for the value of VDAC with respect to b1 and b0 for the MDAC 18.
The MDAC 18 generates Vres by subtracting VDAC from VI with an adder 40 and amplifying the summed value with an amplifier 42 having a gain of two. With additional reference to FIG. 3, the characteristics of the MDAC 18 are illustrated. FIG. 3 graphs VI versus Vres and illustrates the values of b1 and b0 over the range of values for VI.
The last stage 30 is a two bit analog to digital converter (ADC) for converting the last stage""s input voltage, VI, into a two bit digital value. Therefore, similar to the MDACs 18, the last stage has two digital outputs 32, 34 respectively providing b1 and b0. The b0 provided at the second digital output 34 for the last stage 30 represents the least significant bit of the digital output of the A/D converter 10. Alternatively, the last stage 30 can be implemented with an MDAC 18 without connecting the output 22 to any other stage. Table 3 is a definition table for the values of b1 and b0 with respect to VI for the two bit last stage 30.
The digital outputs of the MDACs 18 and the last stage 30 are input into a digital logic correction circuit 44. The digital logic correction circuit 44 generates the digital output, DOUT, of the A/C converter 10. The digital output is a series of bits, or DNxe2x88x921 to D0. In the example, N is four bits. Therefore, the digital output is D3, D2, D1 and D0 where D3 is the most significant bit (MSB) and D0 is the least significant bit (LSB). The digital logic correction circuit 44 corrects error caused by inaccurate thresholds in the 1.5 bit ADC 36 of the MDACs 18 and the two bit ADC of the last stage 30. As long as the individual thresholds deviate no more than Vr/4 from an ideal value, then the error can be corrected by adding shifted digital outputs of each of the stages.
FIG. 4 depicts a shifting operation of the digital error correction circuit 44. It is noted that S is the number of stages of the A/D converter 10 excluding the SHA 14 and the last stage 30. In other words, S is the number of MDACs 18 in the pipeline A/D converter 10.
FIG. 5 is a graph of the characteristics of the 4-bit A/D converter 10 illustrated in FIG. 1, under the condition that the thresholds for the 1.5 bit ADC 36 of the MDACs 18 and the 2 bit ADC of the last stage 30 deviate no more than Vr/4. It is noted that xc2x1VR is the full scale range of the A/D converter 10. It is also noted that an analog input voltage of zero volts is defined as the center of digital 1000. However, if the thresholds of the two bit ADC of the last stage 30 are +Vr*xc2xe, +Vr/4 and xe2x88x92Vr/4, rather than the thresholds shown in Table 3, the A/D conversion curve illustrated in FIG. 5 will move one LSB to the right resulting in analog input voltage of zero volts being defined as the center of digital 0111.
Referring to FIGS. 2 and 13, the timing of the A/D converter 10 will be discussed. The A/D converter 10 has a bias and reference generator (not shown) and a clock generator (not shown). The bias and reference generator generates appropriate bias currents and voltage references for use by the various stages of the A/D converter 10. The clock generator generates a two phase nonoverlapping clock signal, the respective clock pulse signals of which are referred to as CLK1 and CLK2. Waveforms for the two clock pulse signals, CLK1 and CLK2, are illustrated in the top portion of FIG. 13. CLK1 effectively has about a 50% duty cycle. CLK2 also effectively has about a 50% duty cycle but lags CLK1 by 180xc2x0.
As illustrated in FIG. 2, CLK1 is applied to a sample clock input SA of the SHA 14 and a hold clock input H of the amplifier 42 of MDAC1. CLK2 is applied to a hold clock input H of the SHA 14, a latch clock input L of the ADC 36 of MDAC1 and a sample clock input SA of the amplifier 42 of MDAC1. As indicated by FIG. 13, the same clock signals are used for MDAC2, but the clock signals are alternated. More specifically, CLK1 is applied to the latch clock input L of the ADC 36 of MDAC2 and the sample clock input SA of the amplifier 42 of MDAC2 and CLK2 is applied to the hold clock input H of the amplifier 42 of MDAC2. If additional MDAC 18 stages are present for a higher resolution A/D converter 10, the third and subsequent MDACs 18 alternately use CLK1 and CLK2 for the sample/latch operation and the hold operation so that the sample/latch of the MDAC 18 coincides with the hold of the previous MDAC 18. CLK2 is applied to a latch clock input of the last stage 30. It is noted that the last stage 30 does not conduct sample and/or hold operations since the last stage 30 does not generate a residue output.
The sample, hold and latch operations of the SHA stage 14, MDAC1, MDAC2, and the last stage 30 are illustrated in the bottom portion of FIG. 13. The different shading in the timing diagram represents the pipeline conversion process on a series of two analog input samples as the samples pipeline through all of the stages. The SHA 14 samples the analog input signal, VIN, during CLK1 and conducts a hold operation during CLK2. MDAC1 samples Vs/h during CLK2. The ADC 36 of MDAC1 operates during the pulse of CLK2 and preferably latches the digital output on the falling edge of CLK2, thereby giving Vs/h time to settle to the analog equivalent of N bit accuracy. Therefore, the tolerance of the SHA 14 is the analog equivalent of one LSB. MDAC1 generates and holds the residue output Vres1 during CLK1. MDAC2 samples Vres1 during CLK1 and latches its digital output at the end of CLK1, or on the falling edge of CLK1, thereby giving Vres time to settle to the analog equivalent of Nxe2x88x921 bit accuracy. MDAC2 generates and holds Vres2 during CLK2. The last stage 30 latches its digital output at the end of CLK2, or on the falling edge of CLK2, thereby giving Vres2 time to settle to the analog equivalent of Nxe2x88x922 bit accuracy.
Referring to FIG. 14, the conventional digital logic correction (DLC) circuit 44 will be described. The traditional DLC circuit 44 of an N-bit pipeline A/D converter 10 has a series of delays, or shift registers, to delay the digital output of each MDAC stage 18 and the last stage 66 so that their respective digital outputs can be combined as illustrated in FIG. 4. Each delay is provided with a digital input 164 and a digital output 166. It is noted that for simplicity and clarity the illustrated DLC circuit 44 in FIG. 14 shows multiple digital outputs (labeled with the bm1 and bm0 convention discussed above) of each digital output producing stage fed through one series of delays 160. However, in actual implementation separate series of delays 160 are required for each digital output bit for each stage. The number of digital outputs per A/D converter 10 stage will be referred to herein as B-bits per stage. The total number of delays 160 required by the conventional DLC circuit 44 of an N-bit pipeline A/D converter 10 where each stage of the A/D converter 10 has B digital output bits can be computed by the following equation.       Number    ⁢          xe2x80x83        ⁢    of    ⁢          xe2x80x83        ⁢    Delays    =            B      ⁡              (                  1          +          2          +          …          +          N                )              =                  B        ⁡                  (                      N            +            1                    )                    ⁢              (                  N          2                )            
Each delay is provided with a clock input 168 and a reset input (not shown). The same clock signal is applied to a clock input 168 of each delay 160 in the DLC circuit 44. However, as illustrated in FIG. 14, every other delay 160 for any particular A/D converter 10 stage has an inverted clock input 168. Therefore, the digital data output of each A/D converter 10 stage is delayed twice for each clock period. A 10-bit A/D converter 10 is illustrated in FIG. 14. Therefore, the digital output of MDAC1 is delayed a total of nine times or 4.5 clock cycles. After the digital outputs of each stage have been delayed, they are combined as described above and illustrated in FIG. 4 by an adder 168. The adder 168 outputs the digital representation of the analog input signal, or DOUT. The example 10-bit A/D converter 10 requires a total of ninety delays 160.
Should additional information be desired regarding conventional pipeline A/D converters, attention is directed to Stephen H. Lewis et al., xe2x80x9cA Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter,xe2x80x9d IEEE J. Solid-State Circuits, vol. Sc-22, no. 6, pages 954-961, December 1987; Stephen H. Lewis et al., xe2x80x9cA 10-b 20-Msample/s Analog-to-Digital Converter,xe2x80x9d IEEE J. Solid-State Circuits, vol. 27, no. 3, pages 351-358, March 1992; Thomas B. Cho et al., xe2x80x9cA 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter,xe2x80x9d IEEE J. Solid-State Circuits, vol. 30, no. 3, pages 166-172, March 1995; Krishnaswamy Nagaraj et al., xe2x80x9cA 250-mW, 8-b, 52-Msample/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers,xe2x80x9d IEEE J. Solid-State Circuits, vol. 32, no. 3, pages 312-320, March 1997; and Yuh-Min Lin et al., xe2x80x9cA 13-b 2.5-MHZ Self-Calibrated Pipelined A/D Converter in 3-xcexcm CMOS,xe2x80x9d IEEE J. Solid-State Circuits, vol. 26, no. 4, pages 628-636, April 1991, each of which are incorporated by reference in their entireties.
The present invention provides a digital logic correction (DLC) circuit for a pipeline analog to digital (A/D) converter. The A/D converter having a plurality of stages, each stage producing at least a pair of digital output bits from which a digital representation of an analog input signal can be obtained. The DLC circuit has an adder, the adder having a plurality of inputs and an output. The DLC circuit has a plurality of digital delay sets, each digital delay set comprising at least one digital delay, an input of the digital delay set receiving a corresponding digital output bit and an output of the delay set providing a delayed digital output bit to a respective adder input. The DLC circuit has a clock generator, the clock generator providing clock signals to the DLC circuit to synchronize the arrival of the output of each digital delay set at the adder inputs during a data-valid-period. A primary clock signal is applied to the digital delay sets for every other stage. A secondary clock signal is applied to the remaining digital delay sets. The timing of the primary and secondary clock signals being effective to delay the digital output bits of each stage via the respective digital delay sets to cause the digital output bits to arrive at the adder inputs during the data-valid-period so that the adder produces the digital representation of the analog input signal at the adder output.